LPDDR Flash: Enabling Automotive Electrical and Electronic (E/E) Architectures

Engineers are working to strike the right balance between domain and zonal architectures to handle the increasing complexity of modern vehicles while meeting efficiency and performance goals. As processors move to advanced technology nodes to support real-time processing, the need for a high performance external non-volatile memory (NVM) becomes critical.

Flash memory with a standard SPI interface is not fast enough for this application, leading to the invention of Low-Power Double Data Rate (LPDDR) Flash. LPDDR Flash combines—for the first time—an LPDDR interface with an NVM, providing a solution to bridge the performance gap and enable next generation vehicle architectures.

In this article, we’ll look at the memory needs in next gen electrical/electronic (E/E) architectures and see how an industry-first approach to LPDDR Flash provides a solution.

E/E architecture refers to the system of hardware, software, network communication, and wiring integrated into modern vehicles. That system then controls the various vehicle functions, ranging from infotainment to vehicle control. In general, E/E architectures are evolving from single-purpose electronic control units (ECU) to domains and zones that combine many applications into a single function or location.

As illustrated below in Figure 1, domain architectures group vehicle systems by function, such as telematics, infotainment, advanced driver assistance systems (ADAS), and vehicle motion control.

There are also hybrid domain/zone architectures, where the central car computer combines domains for infotainment, ADAS, and vehicle control with some aspects of a zonal architecture.

Notice that not only does the computational demand grow from domain to zonal architecture, but scalability and the use of pooled computational resources does as well. Figure 2 provides a more detailed view of zonal architecture.

Notice that smart sensors/actuators are connected and managed by a zone ECU. The entire system is based on a combination of a central controller with multiple zone controllers.

This shift to zonal architecture is taking place for four key reasons:

All that said, some memory challenges need to be addressed to make this shift an efficient, reliable, and economic reality.

Implementing advanced domain and zonal architecture involves several complex challenges, starting with the task of combining and integrating many different functions into a single real-time processor. Most safety-critical functions operate in a real-time environment and must be highly reliable and capable of making decisions within a finite time.

These combined requirements create a potential barrier, namely, how to meet processing requirements with existing SoC/memory solutions. In addition, growing system complexity leads to increased code size, requiring more embedded Flash (eFlash, not to be confused with external Flash), and embedded SRAM (eSRAM).

eFlash has traditionally been employed for code execution in these situations, and most current real-time processors contain some embedded non-volatile memory (eNVM).

At advanced process nodes, however, automotive-qualified eNVM can be costly—due to die area and scalability. Combined with the challenges identified earlier, NVM for domain and zone controllers need to offer:

With standard xSPI NOR performance typically capped at 200 MHz DDR (400 MB/s), a new category of NVM is required to meet the needs of real-time processors in these applications.

The LPDDR interface is a well-established and proven standard for DRAM. The signaling and protocol offers several advantages, such as:

These advantages are needed to be an interface for a high-performance external NVM. Figure 3 below compares the SoC/memory architecture for code execution from eFlash vs. external LPDDR Flash.

Figure 3. Storage evolution in embedded systems.

Infineon’s new SEMPER X1 LPDDR Flash (Figure 4) combines a high-performance LPDDR interface with a low-latency NOR Flash memory array to deliver the performance demanded by real-time applications.

Figure 4. Infineon SEMPER X1 NOR Flash

It starts by bridging the performance gap currently hampering the use of traditional NOR Flash in advanced E/E architecture by adopting LPDDR4’s interface and signaling. The LPDDR Flash enables real-time code execution with 8x higher bandwidth and 20x faster random read performance compared to today’s fastest xSPI NOR Flash, making the SEMPER X1 a considerable choice for engineers designing domain and zone controllers.

The SEMPER X1 LPPDR Flash is also optimized for code execution, offering 100x faster training time compared to a typical LPDDR4 DRAM. Combined with a bandwidth of 3.2 GB/s, this allows systems to come online immediately, a necessary feature for many automotive applications. Its multi-bank architecture and 5x faster random-access time, make it a match for multi-core real-time processors performing more than one function.

The device also features a multi-bank memory architecture for over-the-air (OTA) updates with zero downtime. Updates can be downloaded to inactive banks while the system simultaneously runs code from active bank(s). Zero downtime updates improve customer experience by eliminating service visits, and increase safety and security by ensuring urgent updates are delivered quickly.

Infineon SEMPER X1 LPPDR Flash is ISO26262 ASIL-B compliant (ASIL-D Ready) for automotive use, and ready for engineers to integrate into their end systems.

Moving to an advanced E/E architecture comes with many challenges, but memory does not have to be one of them. Infineon’s SEMPER X1 LPDDR Flash is an industry-first and is designed to empower engineers to design automobiles of the future.

All images used courtesy of Infineon

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